The present invention relates in general to information storage systems, and more particularly, to a method and apparatus for implementing run length limited codes in partial response channels in a digital magnetic recording system.
In digital magnetic recording systems, data is recorded in a moving magnetic media layer by a storage, or "write" electrical current-to-magnetic field transducer, or "head", positioned immediately adjacent thereto. The data is stored or written to the magnetic media by switching the direction of flow of a substantially constant magnitude write current which flows through windings in the write transducer. Each write current direction transition results in a reversal of the magnetization direction in that portion of the magnetic media just passing by the transducer during current flow in the new direction, with respect to the magnetization direction in the media induced by the previous current flow in the opposite direction. In one scheme, a magnetization direction reversal over a portion of the media moving past the transducer represents a binary digit "1", and the lack of any reversal in that portion represents a binary digit "0".
When data is to be recovered, a retrieval, or "read" magnetic field-to-voltage transducer, (which may be the same as the write transducer if both are inductive) is positioned to have the magnetic media, containing previously stored data, pass thereby such that flux reversal regions in that media either induce, or change a circuit parameter to provide, a voltage pulse to form an output read signal for that transducer. In the scheme described above, each such voltage pulse due to the magnetizations in corresponding media portions represents a binary digit "1" and the absence of a pulse in correspondence with such portions represents a binary digit "0".
In digital magnetic recording systems using peak detection of such voltage pulses as the data recovery method to digitize the read signal, the times between voltage pulses are used to reconstruct the timing information used in recording the data previously stored in the magnetic media to define the path portions described above. More specifically, the output of such a peak detector is used as an input signal to a phase-locked loop forming a controlled oscillator, or phase-lock oscillator (PLO), or synchronizer, which produces an output clock signal from the positions of the detected peaks of the read signal. Absolute time is not used in operating the data retrieval system portion since the speed of the magnetic media varies over time which results in nonuniform time intervals between read signal voltage pulses.
A data encoding scheme known as run-length-limited (RLL) coding is commonly used to improve the PLO's reconstructed clock signal accuracy based on avoiding drift in the frequency thereof because of too much time between voltage read signal pulses. When RLL code is employed, the time durations between read signal voltage pulse transitions is bounded, that is, the number of binary digits of value "0" that can separate binary digits of value "1" in the read signal is limited. This constraint is known overall as a (d,k) constraint where the individual constraint "d" represents the minimum run length of zeros, or the number thereof between ones, while the individual constraint "k" represents the maximum run length of zeros permitted. The "d" portion of the constraint can be chosen so as to avoid crowding of voltage pulses in the read signals which can reduce intersymbol interference problems in which portions of read signal voltage pulses overlap. By limiting the number of consecutive zeros, the "k" constraint maintains the reliability of the PLO in providing an accurate clock signal for the retrieval system. An automatic gain control (AGC) system is used to maintain signal amplitude for the PR4 channel, and the "k" restraint also maintains the reliability of the AGC.
In digital magnetic recording systems employing partial response (PR) signaling, which involves the acceptance of intersymbol interference, data recovery is achieved by periodically sampling the amplitude of the read transducer output signal, as initiated by clock pulses of the PLO, to digitize that signal. In this scheme, each clock pulse of the PLO initiates a sample which has value contributed to it by more than one pulse in the transducer read signal. Thus, a partial response detection system is designed to accommodate the effects of such intersymbol interference, and therefore the "d" constraint may not be necessary (i.e. d=0). The "k" constraint is still necessary in PR signalling because the PLO is still used to provide timing for sampling the read signal, and because the AGC is used to maintain sample amplitude in connection with the PR channel.
A selected frequency response is chosen for the signal channel through which the read signal passes prior to detection thereof, termed a class 4 response, that is particularly suitable for magnetic recording with typical pulse characteristics because the channel requires very little equalization to achieve an overall match of this class 4 response. In a class 4 PR channel for typical pulse characteristics, signal samples are independent of their immediately neighboring samples, but are dependent on samples 2 clock samples away. Therefore, read samples can be divided into 2 subsequences, one of odd indexed samples and one of even indexed samples. Each such subsequence is submitted independently to a Viterbi Algorithm decoder which generates the data that most likely reproduces the original stored values. To limit the delay and increase the accuracy and reliability of the Viterbi Algorithm decoder, another individual constraint, "i", is incorporated in the RLL code for a class 4 partial response channel. The "i" constraint represents the maximum run length of zeros in each subsequence, and the overall constraint for a class 4 PR channel is denoted as (d, k/i), where "d" and "k" represent the same constraints as mentioned above with respect to (d,k) code, and where "d" is set to zero as indicated above.
In order to satisfy the (d, k/i) constraint, "m" data symbols or bits are mapped into "n" code symbols, where "m" is less than "n". The rate of the code to transmit information bits out of the total bits transmitted is given by the formula r=m/n, and for ease of implementation "m" and "n" are usually chosen to be small integers. Since a unit of 8 bits per byte is widely used in the computer and electronic industry, reasonable choices of "m" are 8 and 16. In order to keep the code rate high, "n" is chosen to be equal to "m+1" and so code rates of 8/9 and 16/17 are popular for class 4 partial response channels.
The "m" data symbols, or binary data bits are mapped into the "n" code symbols, or binary data bits, by selecting 2.sup.m different n-bit patterns which satisfy the (d, k/i) constant. Since Boolean logic is used to implement such bit pattern mapping, the larger the "m" and "n" are, the more complex the Boolean logic that is required. In recent years the 8/9 rate for such run length codes has been the most popular rate since it only requires 2.sup.8 or 256 different 9-bit patterns which satisfy the (0, k/i) constraint which simplifies the encoder and decoder Boolean logic required to implement the pattern mapping. However, the 16/17 rate in such codes is 5.8% higher than the 8/9 rate for encoding a given set of data. In order to develop a rate of 16/17 for a (0, k/i) RLL code using such bit pattern mapping to encode the data symbols, there is needed 2.sup.16 or 65,536 17-bit patterns which must satisfy the (0, k/i) constraint. This large number of possible 17-bit codeword combinations requires very complex, and thus undesirable, encoder and decoder logic, compared to the rate 8/9 RLL code. Thus, it would be desirable to provide a 16/17 rate RLL code which is easier to implement than one otherwise obtained through pattern mapping 2.sup.16 possible 17-bit code symbol or codeword combinations.